1. Technical Field
The present invention generally relates to a semiconductor apparatus, and more particularly, to a test circuit of a semiconductor apparatus.
2. Related Art
A semiconductor apparatus, particularly, a DRAM has characteristics of a volatile memory in terms of characteristics of a memory cell including capacitors. Therefore, the DRAM periodically performs a refresh operation in order to retain data stored in the memory cell. Particularly, a refresh operation performed when the DRAM is in a standby mode is called a self-refresh operation. The self-refresh operation is generally performed at a predetermined cycle.
Since the DRAM is less tolerant to temperature, a data retention time of the memory cell changes according to the temperature. Therefore, there are various technologies of changing the self-refresh cycle according to a change in the temperature.
FIG. 1 is a graph illustrating a change in the self-refresh cycle according to a change in the temperature. As illustrated in FIG. 1, since a data retention time is short according to an increase in the temperature, the self-refresh operation should be performed at a short cycle. Also, since the data retention time is long according to a decrease in the temperature, the self-refresh operation may be performed at a long cycle.
FIG. 2 is a diagram schematically illustrating the configuration of a self-refresh signal generation apparatus in the conventional art. In FIG. 2, the self-refresh signal generation apparatus includes a temperature detection unit 10, an erroneous operation prevention unit 20, and a refresh cycle adjustment unit 30. The temperature detection unit 10 detects the temperature of a semiconductor apparatus and generates temperature information NFLAG<0:n>. The erroneous operation prevention unit 20 decodes the temperature information NFLAG<0:n> and generates temperature compensation signals TCFLAG<0:n>. The refresh cycle adjustment unit 30 receives the temperature compensation signals TCFLAG<0:n>, changes a cycle of a reference self-refresh signal NSRF, and generates a refresh signal PSRF.
The erroneous operation prevention unit 20 also includes a latch section (not shown), an update time decision section (not shown), a latch initialization section (not shown) and the like in order to receive the temperature information NFLAG<0:n> generated by the temperature detection unit 10 and generate the normal temperature compensation signals TCFLAG<0:n>. That is, the erroneous operation prevention unit performs a function of filtering the temperature information abnormally generated.